The need for greater functionality and performance in semiconductor devices has resulted in the development of larger and more complex chips. In addition, it is often desirable to include several different functions on a single chip to obtain a “system-on a chip,” which generally results in both an increased chip size and a more complicated manufacturing process. These factors both tend to depress manufacturing yield. It is estimated that many such complex chips, with areas greater than 400 mm2, will generally have very poor manufacturing yield (perhaps under 10%).
One method of maintaining acceptable yields is to manufacture smaller chips, and then to interconnect those chips using lateral and vertical connections on the chips or on support substrates. The interconnected chips thus form a single larger chip which is mounted on another chip, on a substrate or on a chip carrier. Besides improved manufacturing yield, another major advantage of this approach is that the individual chips may be of different sizes, perform different functions, or be fabricated by different or incompatible methods.
A system constructed according to this approach is illustrated schematically in FIG. 1A. The substrate or bottom chip 11 has several chips 10 mounted thereon, with lateral spacing Δx and Δy. For example, the bottom chip 11 may be a DRAM chip while the four chips 10 are processor (“processor engine” or PE) chips.
To realize the advantages offered by the system-on-a-chip (SOC) concept, the different chips are preferably in very close proximity and have very precise alignment with respect to each other. For example, spacing Δx and Δy between chips 10 is preferably about 50 μm or less.
Chips 10 may be placed on the substrate or bottom chip 11 with very high accuracy (within about 1 μm) by using a stud/via interconnection, shown schematically in FIG. 1B. In FIG. 1B, chip 10 has metal studs 12 formed on the terminal surface of the chip, with a layer 16 of a low-melting-point alloy material deposited on the surface of the stud. Dielectric layer 17 (often designed and fabricated as a multilayer structure of polyimide.), on the surface of bottom chip 11, has embedded therein high-density wiring 18 (generally several levels of Cu conductors, as shown schematically in FIG. 1B), and has electrical joining pads 15 on the surface of layer 17. A dielectric layer 14 overlies the wiring layer 17; layer 14 may be formed of a polyimide material typically used in thin film packaging processing. Layer 14 has vias 13 formed therein (e.g. by reactive-ion etching, by photolithography or by an excimer laser), so that a terminal metal joining pad 15 is at each via bottom. The vias may be formed with a sloped wall angle as a guide for high-accuracy, self-aligned placement of the studs 12 in the vias 13. A thin coating 19 of thermoplastic polymer adhesive may be deposited on the top of the dielectric layer 14, to ensure reliable bonding to the chip surface. Details of this stud/via alignment and joining process are provided in U.S. patent application Ser. No. 09/669,531, entitled “Process for making fine pitch connections between devices and structure made by the process,” the disclosure of which is incorporated herein by reference. The use of self-aligning stud/via interconnections permits a significantly higher wiring density compared to current C4 interconnection schemes.
In the SOC shown in FIG. 1A, the wiring layer extends laterally outside the area of chips 10. External connections are generally made at the perimeter 11a of the top surface of bottom chip 11. The overall size of the SOC therefore limits the space available for wirebonding to make the external connections. It is desirable that the external connections instead be made through the backsides of the chips, so that the connections are not restricted by wirebonding space requirements. Formation of a connection pad (e.g. C4 pad) on the backside 10b of a chip would require that electrical connections be made vertically through the chip body, to the device side (surface 10a) of the chip. Furthermore, building vertical interconnections through a device chip would facilitate vertical stacking of chips, effectively extending the SOC concept to three dimensions.
Accordingly, there is a need for a process for fabricating vertical interconnections in a multi-chip device such as an SOC, which permits three-dimensional chip interconnection and which can be practiced with high manufacturing yield.